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Featured Device Characterization Methods





  1. Micro-LED, Photodetector Characterization ​​
    • Electroluminescence (EL), photoluminescence (PL) spectroscopy
    • Micro-LED or photodetector (PD, APD) pixel array variability and statistics
  2. Charge-Pumping Method
    • MOSFET interface trap density before and after bias temperature stress
    • Trap emission time constant determination
  3. Capacitance-Voltage Method
    • MOSFET or MOS-Cap channel or surface doping density, flat-band voltage, oxide thickness, interface trap density and threshold voltage
    • Planar/Fin/GAA FET gate-source/drain overlap capacitance, gate-body capacitance, gate-channel capacitance, source/drain-body capacitance etc
    • Doping depth profile of n+/p or p+/n junctions and Schottky diode
  4. Gate-Controlled Diode Method
    • Leakage current analysis of diode junction, gate-induced junction and depleted surface
  5. Flash Memory Cell
    • Cell endurance test, i.e. program/erase pulse cycling
    • Adjacent cell program/read disturbs
  6. Accelerated Aging Degradation


About Device Electric Test (E-Test)





A state-of-the-art integrated circuit (IC) contains millions or even billions of individual semiconductor devices such as transistors (FET, BJT), diodes, capacitors, resistors and memory cells etc. It is critical to electrically characterize and optimize the performance of these devices separately. This is accomplished by manufacturing various electric test (e-test) structures in scribe lines between IC dies on silicon or other semiconductor wafers, and by performing on-wafer probing to measure their device parameters. These e-test structures are called scribe line monitors (SLM) or process control monitors (PCM).

The SLMs are of great importance to IC technology development because they are the earliest testable devices available as soon as the first metal layer is formed on the first silicon. In production e-test, device parameters are routinely obtained via high-speed automated spot measurements. Each spot measurement retrieves a set of electric output signals under a preset of electric input biases. When some device parameters are out of specified limits or IC chips fail to function as expected, engineers and scientists will performed more advanced device characterization of selected e-test structures in laboratory. This typically involves the measurement of series of device output signal curves by sweeping electric input voltages or currents over certain ranges. Sometimes wafer temperature is varied or light illumination is used during measurement. The test structures may be cut for scanning or transmission electron microscopic (SEM or TEM) imaging and other analyses. Systematic data analysis and statistical correlation to wafer process conditions are subsequently carried out. This is a daunting task because a wafer process flow may contain as many as hundreds of fabrication steps. The ultimate goal of device experimental investigation is to understand and identify the root-causes of device defect or failure in either IC design or wafer processing. Once the potential root causes are found, design or process fixes are proposed, executed and validated in the next wafer lots until all device parameters are within specified limits.

For photonic integrated circuit (PIC) devices, electric test has been enhanced by combining with modern optical spectroscopic characterization for the engineering and manufacture of semiconductor lasers, photodetectors, displays, cameras, lighting and optical fiber communication components etc. Direct bandgap semiconductor materials such as III-V and II-IV compounds are used in addition to indirect bandgap silicon and germanium semiconductors.


Helm Scientific
Laboratory: 1680 Toronto Way, Costa Mesa, California 91626, U. S. A
Headquarter: Fountain Valley, CA 92708, U. S. A.
E-mail: Device.Lab@HelmScientific.com
Phone: (714) 9646958